1. Field of the Invention
This invention relates to a multiprocessor system, and, in particular, to a time multiplexed multiprocessing system having equipment for polling computer and memory requests.
2. Description of the Prior Art
Generally in multiprocessor systems, a plurality of computers must compete with each other for access to a main memory since the main memory can generally service only one computer at a given time. One technique to minimize the problem of such simultaneous access is to physically construct the main memory with a number of separate, independent, and relatively small memory sections. A centralized switch is then provided that can connect any memory section to any computer in accordance with the memory section access needs of the computer.
To create the illusion of a single memory, address interleaving as discussed in "Microprogramming in an Intergrated Hardware/Software System", by John V. Sell, COMPUTER DESIGN, January, 1975, page 77-84 places each sequential address in a different memory section. With each memory section operating independently, interference is greatly reduced between the computers accessing the memory. It can be readily seen that the more memory sections provided, the greater the probability that a bidding computer will obtain access to a particular memory section. Address interleaving and the provision of a plurality of memory sections is utilized in part in the present invention.
Various approaches and techniques have been used to interconnect interleaved memory sections with the computers. Some prior art approaches utilize a space division switching arrangement wherein sufficient hard-wire interconnections are provided to provide access between each computer and each memory section. In such arrangements, complicated control circuitry, perhaps including the provision of a controlling computer, is necessary to control the space division switching. The major advantage of space division switching is that many computers may simultaneously utilize different memory sections thereby reducing interference between the computers. However, the space division switching may be extremely expensive and the cost to provide such a network increases rapidly with the number of computers and/or memory sections.
Other prior art approaches utilize a time multiplexed bus to interconnect the computers with the memory sections. Such an approach is low cost and the cost increases negligibly as the number of computers and memory sections are increased. In such an arrangement, interface logic having decoders must be provided for each computer and for each memory section. A major problem with time multiplex arrangements is that the system throughput becomes limited by the bus capacity as processors are added.
In time multiplexed multiprocessor systems, the control of data flow from the computers to the memory sections, and vice versa, also requires complex control circuitry. This is especially true, when several processors request simultaneous access to the same memory section. Various prior art tie breaking and arbitration arrangements have been proposed to allocate such computer access.
Although prior art arrangements for arbitrating computer requests operate satisfactorily, the cost of such approaches, in both hardware and software, as well as subsequent maintenance costs is expensive especially when additional computers and memory sections are added to the multiprocessor system.